DDR4 SDRAM MT40A2G4
MT40A1G8
MT40A512M16
Features
•V DD = V DDQ = 1.2V ±60mV
•V PP = 2.5V, –125mV, +250mV
•On-die, internal, adjustable V REFDQ generation •1.2V pseudo open-drain I/O
•Refresh time of 8192-cycle at T C temperature range:–64ms at -40°C to 85°C
–32ms at >85°C to 95°C
–16ms at >95°C to 105°C
•16 internal banks (x4, x8): 4 groups of 4 banks each •8 internal banks (x16): 2 groups of 4 banks each •8n-bit prefetch architecture
•Programmable data strobe preambles
•Data strobe preamble training
•Command/Address latency (CAL)•Multipurpose register READ and WRITE capability •Write leveling
•Self refresh mode
•Low-power auto self refresh (LPASR)•Temperature controlled refresh (TCR)
•Fine granularity refresh
•Self refresh abort
•Maximum power saving
•Output driver calibration
•Nominal, park, and dynamic on-die termination (ODT)
•Data bus inversion (DBI) for data bus •Command/Address (CA) parity
•Databus write cyclic redundancy check (CRC)•Per-DRAM addressability
•Connectivity test
•JEDEC JESD-79-4 compliant
•sPPR and hPPR capability Options1Marking •Configuration
– 2 Gig x 42G4
– 1 Gig x 81G8
–512 Meg x 16512M16•78-ball FBGA package (Pb-free) – x4,
x8
–9mm x 13.2mm – Rev. A PM
–8mm x 12mm – Rev. B, D, G WE
–7.5mm x 11mm – Rev. E, H, J SA •96-ball FBGA package (Pb-free) – x16
–9mm x 14mm – Rev. A HA
–8mm x 14mm – Rev. B JY
–7.5mm x 13.5mm – Rev. D, E, H LY
–7.5mm x 13mm – Rev. J TB •Timing – cycle time
–0.625ns @ CL = 22 (DDR4-3200)-062E
–0.682ns @ CL = 21 (DDR4-2933)-068
–0.750ns @ CL = 19 (DDR4-2666)-075
–0.750ns @ CL = 18 (DDR4-2666)-075E
–0.833ns @ CL = 17 (DDR4-2400)-083
–0.833ns @ CL = 16 (DDR4-2400)-083E
–0.937ns @ CL = 15 (DDR4-2133)-093E
– 1.071ns @ CL = 13 (DDR4-1866)-107E •Operating temperature
–Commercial (0° ื T Cื 95°C)None
–Industrial (–40° ื T Cื 95°C)IT
–Automotive (–40° ื T Cื 105°C)AT •Revision:A, :B, :D, :E,
:G, :H, :J Note: 1.Not all options listed can be combined to
define an offered product. Use the part
catalog search on www.micron
for available offerings.
Table 1: Key Timing Parameters
Functional Description
The DDR4 SDRAM is a high-speed dynamic random-access memory internally config-ured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devi-ces, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16devices. The device uses double data rate (DDR) architecture to achieve high-speed op-eration. DDR4 architecture is essentially an 8n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for a device module effectively consists of a single 8n -bit-wide, four-clock-cycle-data transfer at the internal DRAM core and eight corresponding n -bit-wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst-oriented. Accesses start at a selected lo-cation and continue for a burst length of eight or a chopped burst of four in a program-med sequence. Operation begins with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BG[1:0]select the bank group for x4/x8, and BG0 selects the bank group for x16; BA[1:0] select the bank, and A[17:0] select the row. See the Addressing section for more details). The address bits registered coincident with the READ or WRITE command are used to
select the starting column location for the burst operation, determine if the auto PRECHARGE command is to be issued (via A10), and select BC4 or BL8 mode on-the-fly (OTF) (via A12) if enabled in the mode register.
Prior to normal operation, the device must be powered up and initialized in a prede-fined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation.NOTE: The use of the NOP command is allowed only when exiting maximum power saving mode or when entering gear-down mode.
8Gb: x4, x8, x16 DDR4 SDRAM
Functional Description
质量等级领域：宇航级IC 、特军级IC 、超军级IC 、普军级IC 、禁运IC 、工业级IC，军级二三极管，功率管等;
Maximum power savings mode , Per-DRAM addressability mode, and CA parity latency mode
The mode register contents can be changed using the same command and timing re-quirements during normal operation as long as the device is in idle state; that is, all banks are in the precharged state with t RP satisfied, all data bursts are completed, and CKE is HIGH prior to writing into the mode register. If the R TT(NOM) feature is enabled in the mode register prior to and/or after an MRS command, the ODT signal must contin-uously be registered LOW, ensuring R TT is in an off state prior to the MRS command. The ODT signal may be registered HIGH after t MOD has expired. If the R TT(NOM) feature is disabled in the mode register prior to and after an MRS command, the ODT signal can be registered either LOW or HIGH before, during, and after the MRS command. The mode registers are divided into various fields depending on functionality and modes.
In some mode register setting cases, function updating takes longer than t MOD. This type of MRS does not apply t MOD timing to the next valid command, excluding DES. These MRS command input cases have unique MR setting procedures, so refer to indi-vidual function descriptions.
Mode Register 0
Mode register 0 (MR0) controls various device operating modes as shown in the follow-
ing register definition table. Not all settings listed may be available on a die; only set-
tings required for speed bin support are available. MR0 is written by issuing the MRS
command while controlling the states of the BG x, BA x, and A x address pins. The map-
ping of address pins during the MRS command is shown in the following MR0 Register
Definition table.
s.h.e mvTable 7: MR0 Register Definition (Continued)
Notes: 1.Not allowed when 1/4 rate gear-down mode is enabled.
2.If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28
clocks and RTP should be set to 14 clocks.
Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order.
The ordering of accesses within a burst is determined by the burst length, burst type,
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