T op View
SOP
VCCX A10DQ7DQ6DQ5DQ4DQ3
A2A1A0DQ0DQ1DQ2VSS
12345678910111213141516
323130292827
26252423222120191817
PowerStore  32K x 8 nvSRAM
Pin Configuration
Pin Description
Signal Name Signal Description A0 - A14Address Inputs DQ0 - DQ7Data In/Out E Chip Enable G Output Enable W Write Enable
VCCX Power Supply Voltage VSS Ground VCAP Capacitor
HSB
Hardware Controlled Store/Busy
!High-performance CMOS non-volatile static RAM 32768 x 8 bits !25, 35 and 45 ns Access Times !10, 15 and 20 ns Output Enable Access Times
!I CC  = 15 mA typ. at 200 ns Cycle Time
!
Automatic STORE to EEPROM on Power Down using external capacitor
!
Hardware or Software initiated STORE
(STORE Cycle Time < 10 ms)!Automatic STORE Timing
!105 STORE cycles to EEPROM !10 years data retention in EEPROM
!Automatic RECALL on Power Up !Software RECALL Initiation (RECALL Cycle Time < 20 µs)!Unlimited RECALL cycles from EEPROM
!Single 5 V ± 10 % Operation !
Operating temperature ranges:
0to 70 °C -40to 85 °C
-40/-55to 125 °C (only 35 ns)!QS 9000 Quality Standard !ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)!
Packages: SOP32 (300 mil),PDIP32 (600 mil, only C/K-Type)
The U634H256 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disab-led.
The U634H256 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resi-des in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 100 µF capacitor.
Transfers from the EEPROM to the SRAM (the RECALL operation)take place automatically on power up.
The U634H256 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity.
STORE cycles also may be initia-ted under user control via a soft-ware sequence or via a single pin (HSB).
Once a STORE cycle is initiated,further input or output are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted.
RECALL cycles may also be initia-ted by a software sequence.
Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvola-tile information is transferred into the SRAM cells.
The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.
PDIP Features
Description
Operating Mode E HSB W
G
DQ0 - DQ7Standby/not selected
H H *
*
High-Z Internal Read
L
H H H High-Z
Read L H H L
Data Outputs Low-Z Write
L
H
L
*
Data Inputs High-Z
Truth Table for SRAM Operations
Block Diagram
Absolute Maximum Ratings a Symbol Min.Max.Unit Power Supply Voltage V CC -0.57V Input Voltage V I -0.3V CC +0.5V Output Voltage V O -0.3
V CC +0.5
V Power Dissipation P D 1
W Operating Temperature
C-Type K-Type A-Type M-Type
T a
0-40-40-557085125125°C °C °C °C Storage Temperature
T stg
-65
150
°C
Characteristics
All voltages are referenced to V SS  = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V I ,as  well  as
input levels of V IL  = 0 V and V IH  = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t dis -times and t en -times, in which cases transition is measured ± 200 mV from steady-state voltage.
*H or L
a: Stresses greater than those listed under …Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating  only, and functional operation of the device at condition above those indicated in the operational sections of this specification is  not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
EEPROM Array 512 x (64 x 8)
STORE
RECALL
SRAM Array 512 Rows x 64 x 8 Columns
A0 - A13
Store/Recall
Control
HSB
R o w  D e c o d e r
V CCX V SS V CAP
G
E W
Software Detect
Power Control
V CCX V CAP
A5A6A7A8A9A11A12A13DQ0DQ1
DQ2DQ3DQ4DQ5DQ6DQ7
Column I/O Column Decoder
A0 A 1 A2 A3 A4A10
I n p u t  B u f f e r s
A14
DC Characteristics Symbol Conditions
C-Type K-Type A/M-Type
Unit Min.Max.Min.Max.Min.Max.
Operating Supply Current c I CC1V CC
V IL
V IH
t c
t c
t c = 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
= 35 ns
= 45 ns
95
75
65
100
80
70
-
80
-
mA
mA
mA
s.h.e mvAverage Supply Current during STORE c I CC2V CC
E
W
V IL
V IH
= 5.5 V
≤ 0.2 V
≥ V CC-0.2 V
≤ 0.2 V
≥ V CC-0.2 V
677mA
Average Supply Current during PowerStore Cycle I CC4V CC
V IL
V IH
= 4.5 V
= 0.2 V
≥ V CC-0.2 V
444mA
Standby Supply Current d (Cycling TTL Input Levels)I CC(SB)1V CC
E
t c
t c
t c
= 5.5 V
= V IH
= 25 ns
= 35 ns
= 45 ns
40
36
33
42
38
35
-
38
-
mA
mA
mA
Operating Supply Current
at t cR = 200 ns c
(Cycling CMOS Input Levels)I CC3V CC
W
V IL
V IH
= 5.5 V
≥ V CC-0.2 V
≤ 0.2 V
≥ V CC-0.2 V
202020mA
Standby Supply Curent d (Stable CMOS Input Levels)I CC(SB)V CC
E
V IL
V IH
= 5.5 V
≥ V CC-0.2 V
≤ 0.2 V
≥ V CC-0.2 V
334mA
Recommended
Operating Conditions
Symbol Conditions Min.Max.Unit Power Supply Voltage b V CC  4.5  5.5V
Input Low Voltage V IL -2 V at Pulse Width
10 ns permitted
-0.30.8V
Input High Voltage V IH  2.2V CC+0.3V b:V CC reference levels throughout this datasheet refer to V CCX if that is where the power supply connection is made, or V CAP if V CCX is con-nected to ground.
c:I CC1 and I CC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current I CC1 is measured for WRITE/READ - ratio of 1/2.
I CC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d:Bringing E ≥ V IH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION able.
The current I CC(SB)1 is measured for WRITE/READ - ratio of 1/2.
No.Switching Characteristics
Read Cycle
Symbol253545
Unit
Alt.IEC Min.Max.Min.Max.Min.Max.
1Read Cycle Time f t AVAV t cR253545ns 2Address Access Time to Data Valid g t AVQV t a(A)253545ns 3Chip Enable Access Time to Data Valid t ELQV t a(E)253545ns 4Output Enable Access Time to Data Valid t GLQV t a(G)101520ns 5  E HIGH to Output in High-Z h t EHQZ t dis(E)101315ns 6G HIGH to Output in High-Z h t GHQZ t dis(G)101315ns 7  E LOW to Output in Low-Z t ELQX t en(E)555ns 8G LOW to Output in Low-Z t GLQX t en(G)000ns 9Output Hold Time after Address Change t AXQX t v(A)333ns 10Chip Enable to Power Active e t ELICCH t PU000ns 11Chip Disable to Power Standby d, e t EHICCL t PD253545ns SRAM Memory Operations
e:Parameter guaranteed but not tested.
f:
g:
h:Measured ± 200 mV from steady state output voltage.
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V IL , W = V IH )f
Read Cycle 2: G-, E-controlled (during Read cycle: W = V IH )g
No.
Switching Characteristics Write Cycle Symbol
253545
Unit
Alt. #1Alt. #2IEC Min.Max.Min.Max.Min.Max.12Write Cycle Time t AVAV t AVAV
t cW 253545ns 13Write Pulse Width
t WLWH
t w(W)202530ns 14Write Pulse Width Setup Time t WLEH
t su(W)202530ns 15Address Setup Time
t AVWL t AVEL t su(A)000ns 16Address Valid to End of Write t AVWH t AVEH t su(A-WH)202530ns 17Chip Enable Setup Time t ELWH
t su(E)202530ns 18Chip Enable to End of Write t ELEH
t w(E)202530ns 19Data Setup Time to End of Write t DVWH t DVEH t su(D)101215ns 20Data Hold Time after End of Write t WHDX t EHDX t h(D)000ns 21Address Hold after End of Write t WHAX t EHAX t h(A)0
ns 22W LOW to Output in High-Z h, i t WLQZ t dis(W)10
13
15
ns 23W HIGH to Output in Low-Z
t WHQX
t en(W)
5
55ns
Ai Ai E G I CC
DQi
Output
DQi
Output