TL H 10399MF10Universal Monolithic Dual Switched Capacitor Filter
December 1994
MF10
Universal Monolithic Dual Switched Capacitor Filter
General Description
The MF10consists of 2independent and extremely easy to use general purpose CMOS active filter building blocks Each block together with an external clock and 3to 4resis-tors can produce various 2nd order functions Each building block has 3output pins One of the outputs can be config-ured to perform either an allpass highpass or a notch func-tion the remaining 2output pins perform lowpass and band-pass functions The center frequency of the lowpass and bandpass 2nd order functions can be either directly depen-dent on the clock frequency or they can depend on both clock frequency and external resistor ratios The center fre-quency of the notch and allpass functions is directly depen-dent on the clock frequency while the highpass center fre-quency depends on both resistor ratio and clock Up to 4th order functions can be performed by cascading the two 2nd order building blocks of the MF10 higher than 4th order functions can be obtained by cascading MF10packages
Any of the classical filter configurations (such as Butter-worth Bessel Cauer and Chebyshev)can be formed
For pin-compatible device with improved performance refer to LMF100datasheet
Features
Y Easy to use
Y Clock to center frequency ratio accuracy g 0 6%
Y
Filter cutoff frequency stability directly dependent on external clock quality
Y Low sensitivity to external component variation
Y
Separate highpass (or notch or allpass) bandpass low-pass outputs
Y f O c Q range up to 200kHz Y Operation up to 30kHz
Y 20-pin 0 3 wide Dual-In-Line package
Y
20-pin Surface Mount (SO)wide-body package
System Block Diagram TL H 10399–1
Connection Diagram
Surface Mount and Dual-In-Line
Package
TL H 10399–4
Top View
Order Number MF10AJ or MF10CCJ See NS Package Number J20A Order Number MF10ACWM or
MF10CCWM
See NS Package Number M20B Order Number MF10ACN or
MF10CCN
See NS Package Number N20A绿光
C 1995National Semiconductor Corporation RRD-B30M115 Printed in U S A
Absolute Maximum Ratings(Note1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(V a b V b)14V Voltage at Any Pin V a a0 3V
V b b0 3V Input Current at Any Pin(Note2)5mA Package Input Current(Note2)20mA Power Dissipation(Note3)500mW Storage Temperature150 C ESD Susceptability(Note11)2000V Soldering Information
N Package 10sec 260 C J Package 10sec 300 C SO Package Vapor Phase(60Sec )215 C
Infrared(15Sec )220 C See AN-450‘‘Surface Mounting Methods and Their Effect on Product Reliability’’(Appendix D)for other methods of soldering surface mount devices
赐我歌曲Operating Ratings(Note1)
Temperature Range T MIN s T A s T MAX MF10ACN MF10CCN0 C s T A s70 C MF10CCWM MF10ACWM0 C s T A s70 C MF10CCJ b40 C s T A s85 C MF10AJ b55 C s T A s125 C
Electrical Characteristics V a e a5 00V and V b e b5 00V unless otherwise specified Boldface limits apply for T MIN to T MAX all other limits T A e T J e25 C
MF10ACN MF10CCN
MF10CCJ MF10AJ
MF10ACWM MF10CCWM
Symbol Parameter Conditions
Typical Tested Design
Typical
Tested Design Units
(Note8)
Limit Limit
(Note8)
Limit Limit (Note9)(Note10)(Note9)(Note10)
V a b V b Supply Voltage Min99V
Max1414V
I S Maximum Supply Clock Applied to Pins10 11
81212812mA Current No Input Signal
f O Center Frequency Min f O c Q k200kHz0 10 20 10 2Hz
Range Max30203020kHz f CLK Clock Frequency Min5 0105 010Hz
Range Max1 51 01 51 0MHz f CLK f O50 1Clock to MF10A Q e10V pin12e5V g0 2g0 6g0 6g0 2g1 0%
Center Frequency MF10C Mode1f CLK e250kHz
g0 2g1 5g1 5g0 2g1 5% Ratio Deviation
f CLK f O100 1Clock to MF10A Q e10V pin12e0V g0 2g0 6g0 6g0 2g1 0%
Center Frequency MF10C Mode1f CLK e500kHz
g0 2g1 5g1 5g0 2g1 5% Ratio Deviation
Clock Feedthrough Q e10
1010mV
Mode1
Q Error(MAX)Q e10V pin12e5V
g2g6g6g2g10% (Note4)Mode1f CLK e250kHz
V pin12e0V
g2g6g6g2g10%
f CLK e500kHz
H OLP DC Lowpass Gain Mode1R1e R2e10k0g0 2g0 20g0 2dB
V OS1DC Offset Voltage(Note5)g5 0g20g20g5 0g20mV
V OS2DC Offset Voltage Min V pin12e a5V S A B e V a b150b185b185b150b185
mV (Note5)Max(f CLK f O e50)b85b85b85
Min V pin12e a5V S A B e V b b
70b70mV Max(f CLK f O e50)
V OS3DC Offset Voltage Min V pin12e a5V All Modes b70b100b100b70b100
mV (Note5)Max(f CLK f O e50)b20b20b20
一秒的安慰V OS2DC Offset Voltage V pin12e0V S A B e V a b
300b300mV (Note5)(f CLK f O e100)
V pin12e0V S A B e V b b
140b140mV (Note5)(f CLK f O e100)
V OS3DC Offset Voltage V pin12e0V All Modes b
140b140mV (Note5)(f CLK f O e100)
2
Electrical Characteristics(Continued)V a e a5 00V and V b e b5 00V unless otherwise specified Boldface limits apply for T MIN to T MAX all other limits T A e T J e25 C
MF10ACN MF10CCN
MF10CCJ MF10AJ
MF10ACWM MF10CCWM
Symbol Parameter Conditions
Typical Tested Design
Typical
Tested Design Units
(Note8)
Limit Limit
(Note8)
Limit Limit (Note9)(Note10)(Note9)(Note10)
V OUT Minimum Output BP LP Pins R L e5k g4 25g3 8g3 8g4 25g3 8V Voltage Swing N AP HP Pin R
L e3 5k g4 25g3 8g3 8g4 25g3 6V GBW Op Amp Gain BW Product2 52 5MHz
SR Op Amp Slew Rate77V m s
Dynamic Range V pin12e a5V
8383dB (Note6)(f CLK f O e50)
V pin12e0V
8080dB
(f CLK f O e100)
I SC Maximum Output Short Source2020mA
Circuit Current(Note7)Sink3 03 0mA Logic Input Characteristics Boldface limits apply for T MIN to T MAX all other limits T A e T J e25 C
MF10ACN MF10CCN
MF10CCJ MF10AJ
MF10ACWM MF10CCWM
Parameter Conditions
Typical Tested Design
Typical
Tested Design Units
(Note8)
Limit Limit
(Note8)
Limit Limit (Note9)(Note10)(Note9)(Note10)
CMOS Clock Min Logical‘‘1’’V a e a5V V b e b5V a3 0a3 0a3 0V Input Voltage Max Logical‘‘0’’V LSh e0V b3 0b3 0b3 0V
Min Logical‘‘1’’V a e a10V V b e0V a8 0a8 0a8 0V
Max Logical‘‘0’’V LSh e a5V a
2 0a2 0a2 0V
TTL Clock Min Logical‘‘1’’V a e a5V V b e b5V a2 0a2 0a2 0V Input Voltage Max Logical‘‘0’’V LSh e0V a0 8a0 8a0 8V
Min Logical‘‘1’’V a e a10V V b e0V a2 0a2 0a2 0V
Max Logical‘‘0’’V LSh a0 8a0 8a0 8V Note1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions
Note2 When the input voltage(V IN)at any pin exceeds the power supply rails(V IN k V b or V IN l V a)the absolute value of current at that pin should be limited to5mA or less The20mA package input current limits the number of pins that can exceed the power supply boundaries with a5mA current limit to four Note3 The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX i JA and the ambient temperature T A The maximum allowable power dissipation at any temperature is P D e(T JMAX b T A) i JA or the number given in the Absolute Maximum Ratings whichever is lower For this device T JMAX e125 C and the typical junction-to-ambient thermal resistance of the MF10ACN CCN when board mounted is55 C W For the MF10AJ CCJ this number increases to95 C W and for the MF10ACWM CCWM this number is66 C W
三天三夜原唱Note4 The accuracy of the Q value is a function of the center frequency(f O) This is illustrated in the curves under the heading‘‘Typical Performance Characteristics’’
Note5 V OS1 V OS2 and V OS3refer to the internal offsets as discussed in the Applications Information Section3 4
Note6 For g5V supplies the dynamic range is referenced to2 82V rms(4V peak)where the wideband noise over a20kHz bandwidth is typically200m V rms for the MF10with a50 1CLK ratio and280m V rms for the MF10with a100 1CLK ratio
Note7 The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply These are the worst case conditions
Note8 Typicals are at25 C and represent most likely parametric norm
Note9 Tested limits are guaranteed to National’s AOQL(Average Outgoing Quality Level)
Note10 Design limits are guaranteed but not100%tested These limits are not used to calculate outgoing quality levels
Note11 Human body model 100pF discharged through a1 5k X resistor
3
Typical Performance Characteristics
vs Power Supply Voltage
Power Supply Current (N AP HP Output)
vs Load Resistance Positive Output Voltage Swing Resistance (N AP HP Output)
Swing vs Load
Negative Output Voltage Swing vs Temperature Negative Output
vs Temperature Positive Output Swing Frequency
Crosstalk vs Clock Temperature Q Deviation vs Temperature Q Deviation vs Clock Frequency
Q Deviation vs Clock Frequency Q Deviation vs vs Temperature f CLK  f O Deviation vs Temperature
f CLK  f O Deviation TL H 10399–2
4
Typical Performance Characteristics
(Continued)
vs Clock Frequency
f CLK  f O Deviation vs Clock Frequency
f CLK  f O Deviation Deviation of f CLK
f O
vs Nominal Q Deviation of f CLK
f O
vs Nominal Q TL H 10399–3
Pin Descriptions
LP(1 20) BP(2 19) The second order lowpass bandpass N AP HP(3 18)and notch allpass highpass outputs
These outputs can typically sink 1 5mA and source 3mA Each output typically swings to within 1V of each supply
INV(4 17)The inverting input of the summing op-amp of each filter These are high im-pedance inputs but the non-inverting in-put is internally tied to AGND making
INV A and INV B behave like summing junctions (low impedance current in-puts)
S1(5 16)S1is a signal input pin used in the all-pass filter configurations (see modes 4
and 5) The pin should be driven with a source impedance of less than 1k X  If S1is not driven with a signal it should be tied to AGND (mid-supply)
S A B (6)
This pin activates a switch that connects one of the inputs of each filter’s second summer to either AGND (S A B tied to V b )or to the lowpass (LP)output (S A B tied to V a ) This offers the flexibility needed for configuring the filter in its various modes of operation
V A a (7) V D a (8)
Analog positive supply and digital posi-tive supply These pins are internally connected through the IC substrate and therefore V A a and V D a should be de-rived from the same power supply source They have been brought out separately so they can be bypassed by separate capacitors if desired They can be externally tied together and by-passed by a single capacitor
V A b (14) V D b (13)Analog and digital negative supplies
The same comments as for V A a
and V D a
apply here
5
Pin Descriptions(Continued)
LSh(9)Level shift pin it accommodates various
clock levels with dual or single supply
operation With dual g5V supplies the
MF10can be driven with CMOS clock
levels(g5V)and the LSh pin should be
tied to the system ground If the same
supplies as above are used but only TTL
clock levels derived from0V to a5V
supply are available the LSh pin should
be tied to the system ground For single
supply operation(0V and a10V)the
V A b V D b pins should be connected to
the system ground the AGND pin
should be biased at a5V and the LSh
pin should also be tied to the system
ground for TTL clock levels LSh should
be biased at a5V for CMOS clock lev-
els in10V single-supply applications CLKA(10) Clock inputs for each switched capaci-CLKB(11)tor filter building block They should both
be of the same level(TTL or CMOS)
The level shift(LSh)pin description dis-
cusses how to accommodate their lev-
els The duty cycle of the clock should
be close to50%especially when clock
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frequencies above200kHz are used
This allows the maximum time for the
internal op-amps to settle which yields
optimum filter operation
50 100 CL(12)By tying this pin high a50 1clock-to-fil-
ter-center-frequency ratio is obtained
Tying this pin at mid-supplies(i e analog
ground with dual supplies)allows the fil-
ter to operate at a100 1clock-to-cen-
ter-frequency ratio When the pin is tied
low(i e  negative supply with dual sup-
plies) a simple current limiting circuit is
triggered to limit the overall supply cur-
rent down to about2 5mA The filtering
action is then aborted
AGND(15)This is the analog ground pin This pin
should be connected to the system
ground for dual supply operation or bi-
ased to mid-supply for single supply op-
eration For a further discussion of mid-
supply biasing techniques see the Appli-
cations Information(Section3 2) For
optimum filter performance a‘‘clean’’
ground must be provided
1 0Definition of Terms
f CLK the frequency of the external clock signal applied to
pin10or11
f O center frequency of the second order function complex
pole pair f O is measured at the bandpass outputs of the MF10 and is the frequency of maximum bandpass gain (Figure1)
f notch the frequency of minimum(ideally zero)gain at the
notch outputs
f z the center frequency of the second order complex zero
pair if any If f z is different from f O and if Q Z is high it can be observed as the frequency of a notch at the allpass output (Figure10)
Q ‘‘quality factor’’of the2nd order filter Q is measured at the bandpass outputs of the MF10and is equal to f O divided by the b3dB bandwidth of the2nd order bandpass filter (Figure1) The value of Q determines the shape of the2nd order filter responses as shown in Figure6
Q Z the quality factor of the second order complex zero pair if any Q Z is related to the allpass characteristic which is written
H AP(s)e
H OAP s2b s0O Q Z a0O2J
s2a
s0O
Q
a0O2
where Q Z e Q for an all-pass response
H OBP the gain(in V V)of the bandpass output at f e f O
H OLP the gain(in V V)of the lowpass output as f x0Hz
(Figure2)
123mutourenH OHP the gain(in V V)of the highpass output as f x
f CLK 2(Figure3)
H ON the gain(in V V)of the notch output as f x0Hz
and as f x f CLK 2 when the notch filter has equal gain above and below the center frequency(Figure4) When the low-frequency gain differs from the high-frequency gain as in modes2and3a(Figures11and8) the two quantities below are used in place of H ON
H ON1 the gain(in V V)of the notch output as f x0Hz
H ON2 the gain(in V V)of the notch output as f x f CLK 2 6