General Description
The MAX3992 is a 10G bps clock and data recovery (CDR) with equalizer IC for XFP optical transmitters. The MAX3992 and the MAX3991 (CDR with limiting amplifier)form a signal conditioner chipset for use in XFP trans-ceiver modules. The chipset is XFI compliant and offers multirate operation for data rates from 9.95G bps to 11.1Gbps.甄子丹资料
The MAX3992 recovers the data for up to 12 inches of FR-4 and one connector without the need for a stand-alone equalizer. The phase-locked loop is optimized for jitter tolerance in SONET, Ethernet, and Fibre-Channel applications. Low jitter generation of 4mUI RMS leaves adequate margin for meeting SONET jitter requirements at the optical output.
An AC-based power detector asserts the loss-of-signal (LOS) output when the input signal is removed. An exter-nal reference clock, with frequency equal to 1/64 or 1/16of the serial data rate, is used to aid in frequency acqui-sition. A loss-of-lock (LOL) indicator is provided to indi-cate the lock status of the receiver PLL.
The MAX3992 is available in a 4mm x 4mm, 24-pin QFN package. It consumes 356mW from a single +3.3V sup-ply and operates over a 0°C to +85°C temperature range.
Applications
9.95Gbps to 11.1Gbps Optical XFP Modules SONET OC-192/SDH STM-64 XFP Transceivers 10.3Gbps/11.1Gbps Ethernet XFP Transceivers 10.5Gbps Fibre-Channel XFP Transceivers 10Gbps DWDM Transceivers 10Gbps XFP Copper Modules
High-Speed Backplane Interconnects
Features
♦Multirate Operation from 9.95Gbps to 11.1Gbps ♦Span Up to 300mm (12in) FR4 with One Connector ♦Low-Output Jitter Generation: 4mUI RMS ♦Low-Output Deterministic Jitter: 4.6ps P-P ♦XFI-Compliant Input Interface ♦LOS Indicator ♦LOL Indicator
♦Power Dissipation: 356mW
MAX3992
10Gbps Clock and Data Recovery
with Equalizer
________________________________________________________________Maxim Integrated Products 1
不说 李荣浩
19-3496; Rev 2; 11/06
For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.
Ordering Information
Typical Application Circuit appears at end of data sheet.氛围音乐
*Future product—contact factory for availability.+Denotes lead-free package.
M A X 3992
10Gbps Clock and Data Recovery with Equalizer 2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
中国好歌曲柳重言Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, V CC ..............................................-0.5V to +4.0V Input Voltage Levels
(SDI+, SDI-, REFCLK+,
REFCLK-)....................................(V CC - 1.0V) to (V CC + 0.5V)CML Output Voltage
(SDO+, SDO-, SCLKO+,
SLCKO-)......................................(V CC - 1.0V) to (V CC + 0.5V)
Voltage at (CFIL, LOL, VTH, POL,
LOS, FCTL1, FCTL2)..............................-0.5V to (V CC + 0.5V)Continuous Power Dissipation (T A = +85°C)
24-Pin QFN (derate 20.8mW/°C above +85°C).........1355mW Junction -40°C to+150°C Storage …………..-55°C to +150°C Lead Temperature (soldering, 10s)..……………………..+300°C
ELECTRICAL CHARACTERISTICS
(See Table 1 for operating conditions. Typical values at V CC = +3.3V, T A = +25°C, unless otherwise noted.)
MAX3992
10Gbps Clock and Data Recovery
再见艳阳天主题曲with Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at V = +3.3V, T = +25°C, unless otherwise noted.)
M A X 3992
10Gbps Clock and Data Recovery with Equalizer 4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at V CC = +3.3V, T A = +25°C, unless otherwise noted.)
Note 1:Measured with 100mV P-P differential amplitude.Note 2:Guaranteed by design and characterization.
Note 3:Measured from the time that the FCTL1 input goes high with FCTL2 = 0, to the time when the supply current drops to less
than 40% of the nominal value.
Note 4:Measured with PRBS = 231 - 1.
Note 5:Larger C FILT can be used to reduce jitter peaking at ≤120kHz. A larger C FILT will increase acquisition time. C FILT should
not exceed 200nF.
Note 6:Measurement limited by test equipment.
Note 7:Jitter tolerance is for BER ≤10-12, measured with additional 0.1VI deterministic jitter through 15 inches of FR4. (See Typical
我是歌手谁是总冠军Operating Characteristics 1.)
Note 8:Measured with 50kHz to 80MHz SONET filter.Note 9:Applies on power-up or after standby.Note 10:Over process, temperature and supply.
Note 11:Hysteresis is defined as 20Log(V LOS-DEASSERT /V LOS-ASSERT ).
MAX3992
10Gbps Clock and Data Recovery
with Equalizer
_______________________________________________________________________________________5
Figure 1. TX LOL Assert and PLL Acquisition Time
Figure 2. LOS Assert/Deassert Time