THC63LVDM83D _Rev.3.1_E
Block Diagram
7THC63LVDM83D
REDUCED SWING LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE
General Description
The THC63LVDM83D transmitter is designed to sup-port pixel data transmission between Host and Flat Panel Display from NTSC up to 1080p(60Hz).
The THC63LVDM83D converts 28bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling)data stream. The transmitter can be programmed for ris-ing edge or falling edge clocks through a dedicated pin.At a transmit clock frequency of 160MHz, 24bits of RGB data and 4bits of timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at an effective rate of 1120Mbps per LVDS channel.
Features
•Wide dot clock range: 8-160MHz suited for NTSC, VGA, SVGA, XGA,SXGA and SXGA+ •PLL requires no external components •Supports spread spectrum clock generator •On chip jitter filtering
•Clock edge selectable
•Supports reduced swing LVDS for low EMI •Power down mode
•Low power single 3.3V CMOS design
•Low profile 56 Lead TSSOP Package
• 1.2 up to 3.3V tolerant data inputs to connect directly to low power,low voltage application and graphic processor.
•
Pin compatible with THC63LVDM83C/83R(24bits)
T T L P A R A L L E L T O S E R I A L
PLL
TA +/-TB +/-TC +/-TD +/-TCLK +/-R/F /PDWN
TA0-6TC0-6TD0-6
TRANSMITTER
(8 to 160MHz)
CMOS/TTL 7
RS
7TB0-67INPUTS CLOCK (LVDS)8-160MHz
DATA (LVDS)(56-1120Mbit/On Each
LVDS Channel)
CLKIN THC63LVDM83D
Pin Out
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 2856 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
RS TD1 TA5 TA6 GND TB0 TB1 TD2 VCC TD3 TB2 TB3 GND TB4 TB5 TD4 R/F TD5 TB6 TC0 GND TC1 TC2 TC3 TD6 VCC TC4 TC5
TA4
TA3
TA2
GND
TA1
TA0
TD0
LVDS GND
TA-
TA+
TB-
TB+
LVDS VCC
LVDS GND
TC-
TC+
TCLK-
TCLK+
TD-
TD+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLK IN
TC6
GND
THC63LVDM83D
Pin Description
Pin Name Pin #Type Description
TA+, TA-47, 48LVDS OUT LVDS Data Out.
TB+, TB-45, 46LVDS OUT TC+, TC-41, 42LVDS OUT TD+, TD-37, 38LVDS OUT TCLK+, TCLK-39, 40
LVDS OUT
LVDS Clock Out.TA0 ~ TA651, 52, 54, 55, 56, 3, 4IN Pixel Data Inputs.TB0 ~ TB66, 7, 11, 12, 14, 15, 19IN TC0 ~ TC620, 22, 23, 24, 27, 28, 30IN TD0 ~ TD650, 2, 8, 10, 16, 18, 25
IN /PDWN
32
IN
H: Normal operation,
L: Power down (all outputs are Hi-Z)RS 1IN
LVDS swing mode, VREF select.See Fig4, 5.R/F 17IN Input Clock Triggering Edge Select.H: Rising edge, L: Falling edge
VCC 9, 26Power Power Supply Pins for TTL inputs and digital circuitry.CLKIN 31IN Clock in.
GND 5, 13, 21,29, 53Ground Ground Pins for TTL inputs and digital circuitry.LVDS VCC 44Power Power Supply Pins for LVDS Outputs.LVDS GND 36, 43, 49
Ground Ground Pins for LVDS Outputs.PLL VCC 34Power Power Supply Pin for PLL circuitry.PLL GND
33, 35
Ground
Ground Pins for PLL circuitry.
RS
LVDS Swing Small Swing Input Support
VCC 350mV N/A 0.6 ~ 1.4V 350mV RS=VREF a
GND
200mV
N/A
a. VREF is Input Reference Voltage.
Absolute Maximum Ratings 1
Supply Voltage (V CC )-0.3V ~ +4.0V CMOS/TTL Input Voltage -0.3V ~ (V CC + 0.3V)CMOS/TTL Output Voltage -0.3V ~ (V CC + 0.3V)LVDS Transmitter Output Voltage -0.3V ~ (V CC + 0.3V)Output Current continuous Junction Temperature +125Storage Temperature Range -55 ~ +150Reflow Peak Temperature / Time +260 / 10sec.Maximum Power Dissipation @+25 1.8W
1.“Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
°C
°C °C °C °C
Electrical Characteristics CMOS/TTL DC Specifications
V CC = 3.0V ~ 3.6V, Ta = 0 ~ +70Notes: 1V DDQ voltage defines max voltage of small swing input.
It is not an actual input voltage. 2 Small swing signal is applied to TA0-6,TB0-6,TC0-6,TD0-6 and CLKIN.
LVDS Transmitter DC Specifications
V CC = 3.0V ~ 3.6V, Ta = 0 ~ +70Symbol Parameter
Conditions
Min.
Typ.Max.Units V IH High Level Input Voltage RS=VCC or GND 2.0V CC V V IL Low Level Input Voltage RS=VCC or GND
GND 0.8V V DDQ 1Small Swing Voltage 1.2
2.8
V
V REF Input Reference Voltage Small Swing (RS=V DDQ /2)V DDQ /2
V SH 2Small Swing High Level Input Voltage
V REF = V DDQ /2V DDQ /2 +100mV
V V SL 2Small Swing Low Level Input Voltage V REF = V DDQ /2V DDQ /2 -100mV
V I INC
Input Current
μA
Symbol
Parameter
Conditions
Min.Typ.Max.Units VOD
Differential Output Voltage
RL=100Ω
Normal swing
RS=V CC 250
350
450
mV
Reduced swing RS=GND
100200300mV
ΔVOD Change in VOD between complementary output states RL=100Ω
35mV VOC Common Mode Voltage 1.125
1.25
1.375V ΔVOC Change in VOC between complementary output states 35mV I OS Output Short Circuit Current VOUT=0V, RL=100Ω-24
mA I OZ
Output TRI-STATE Current
/PDWN=0V, V OUT =0V to V CC μA
°C °C
0V V IN V CC
≤≤10
±°C °C
10
±
Supply Current
V CC = 3.0V ~ 3.6V, Ta = 0 ~ +70 Symbol Parameter Condition(*)Typ.Max.Units
I TCCW Transmitter Supply
1080pmvCurrent
RL=100Ω,CL=5pF
V CC=3.3V, RS=V CC
Worst Case Pattern
f=85MHz6167mA
f=135MHz7783mA
f=160MHz8492mA
RL=100Ω,CL=5pF
V CC=3.3V, RS=GND
Worst Case Pattern
f=85MHz5056mA
f=135MHz6571mA
f=160MHz7380mA
I TCCS Transmitter Power
Down Supply Current /PDWN = L, All Inputs = L or H10μA
°C°C
CLKIN
Tx0
Worst Case Pattern
Tx1
Tx2
Tx3
Tx4
Tx5
Tx6
x= A, B, C, D
Fig1. Worst Case Pattern
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