DS90C383/DS90CF384
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD)Link—65MHz,+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD)Link—65MHz
General Description
The DS90C383transmitter converts 28bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differe
ntial Signal-ing)data streams.A phase-locked transmit clock is transmit-ted in parallel with the data streams over a fifth LVDS link.Every cycle of the transmit clock 28bits of input data are sampled and transmitted.The DS90CF384receiver con-verts the LVDS data streams back into 28bits of LVCMOS/LVTTL data.At a transmit clock frequency of 65MHz,24bits of RGB data and 3bits of LCD timing and control data (FPLINE,FPFRAME,DRDY)are transmitted at a rate of 455Mbps per LVDS data channel.Using a 65MHz clock,the data throughputs is 227Mbytes/sec.The transmitter is of-fered with programmable edge data strobes for convenient interface with a variety of graphics controllers.The transmit-ter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin.A Rising edge trans-mitter will inter-operate with a Falling edge receiver (DS90CF384)without any translation logic.Both devices are also offered in a 64ball,0.8mm fine pitch ball grid array (FBGA)package which provides a 44%reduction in PCB footprint compared to the TSSOP package.
This chipset is an ideal means to solve EMI and cable size problems associated with wide,high speed TTL interfaces.
Features
n 20to 65MHz shift clock support
n Programmable transmitter (DS90C383)strobe select (Rising or Falling edge strobe)n Single 3.3V supply
n Chipset (Tx +Rx)power consumption <250mW (typ)n Power-down mode (<0.5mW total)
n Single pixel per clock XGA (1024x768)ready
n Supports VGA,SVGA,XGA and higher addressability.n Up to 227Megabytes/sec bandwidth n Up to 1.8Gbps throughput
n Narrow bus reduces cable size and cost n 290mV swing LVDS devices for low EMI n PLL requires no external components n Low profile 56-lead TSSOP package.
n Also available in a 64ball,0.8mm fine pitch ball grid array (FBGA)package
n Falling edge data strobe Receiver
n Compatible with TIA/EIA-644LVDS standard n ESD rating >7kV
n Operating Temperature:−40˚C to +85˚C
汪涵 仇晓
Block Diagrams
TRI-STATE ®is a registered trademark of National Semiconductor Corporation.
Typical Application李媛丽
DS012887-2
November 2000
DS90C383/DS90CF384+3.3V Programmable LVDS 24-Bit-Color Flat Panel Display (FPD)Link—65MHz
©2000National Semiconductor Corporation DS012887www.national
Block Diagrams
(Continued)
DS90C383
DS012887-1
Order Number DS90C383MTD or DS90C383SLC See NS Package Number MTD56or SLC64A
DS90CF384
DS012887-24
Order Number DS90CF384MTD or DS90CF384SLC See NS Package Number MTD56or SLC64A
D S 90C 383/D S 90C F 384
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Absolute Maximum Ratings(Note1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage(V CC)−0.3V to+4V CMOS/TTL Input Voltage−0.3V to(V CC+0.3V) CMOS/TTL Output Voltage−0.3V to(V CC+0.3V) LVDS Receiver Input Voltage−0.3V to(V CC+0.3V) LVDS Driver Output Voltage−0.3V to(V CC+0.3V) LVDS Output Short Circuit
Duration Continuous Junction Temperature+150˚C Storage Temperature−65˚C to+150˚C Lead Temperature
(Soldering,4sec for TSSOP)+260˚C Solder Reflow Temperature
(20sec for FBGA)+220˚C Maximum Package Power Dissipation Capacity25˚C
MTD56(TSSOP)Package:
DS90C383MTD  1.63W DS90CF384MTD  1.61W Package Derating:
DS90C383MTD12.5mW/˚C above+25˚C
DS90CF384MTD12.4mW/˚C above+25˚C Maximum Package Power Dissipation Capacity25˚C
SLC64A Package:
DS90C383SLC  2.0W DS90CF384SLC  2.0W Package Derating:
DS90C383SLC10.2mW/˚C above+25˚C DS90CF384SLC10.2mW/˚C above+25˚C
ESD Rating
(HBM,1.5kΩ,100pF)>7kV Recommended Operating Conditions
Min Nom Max Units Supply Voltage(V CC)  3.0  3.3  3.6V Operating Free Air
Temperature(T A)−40+25+85˚C Receiver Input Range0  2.4V Supply Noise Voltage(V CC)100mV PP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS
V IH High Level Input Voltage  2.0V CC V
V IL Low Level Input Voltage GND0.8V
V OH High Level Output Voltage I OH=−0.4mA  2.7  3.3V
V OL Low Level Output Voltage I OL=2mA0.060.3V
V CL Input Clamp Voltage I CL=−18mA−0.79−1.5V
I IN Input Current V IN=V CC,GND,2.5V or0.4V±5.1±10µA
I OS Output Short Circuit Current V OUT=0V−60−120mA
LVDS DC SPECIFICATIONS
V OD Differential Output Voltage R L=100Ω250345450mV
∆V OD Change in V OD between35mV complimentary output states
V OS Offset Voltage(Note4)  1.125  1.25  1.375V
∆V OS Change in V OS between35mV complimentary output states
I OS Output Short Circuit Current V OUT=0V,R L=100Ω−3.5−5mA
I OZ Output TRI-STATE®Current Power Down=0V,±1±10µA
V OUT=0V or V CC
V TH Differential Input High Threshold V CM=+1.2V+100mV
V TL Differential Input Low Threshold−100mV
I IN Input Current V IN=+2.4V,V CC=3.6V±10µA
V IN=0V,V CC=3.6V±10µA TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current R L=100Ω,
C L=5pF,
f=32.5MHz3145mA Worst Case Worst Case Pattern f=37.5MHz3250mA
DS90C383/DS90CF384
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Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ Max Units TRANSMITTER SUPPLY CURRENT
(Figures 1,3),T A =−40˚C to +85˚Cgirlfriend艾薇儿
f =65MHz 4255mA ICCTG
Transmitter Supply Current R L =100Ω,C L =5pF,
f =32.5MHz 2335mA 16Grayscale
16Grayscale Pattern
f =37.5MHz 2840mA (Figures 2,3),T A =−40˚C to +85˚C
f =65MHz
3145mA ICCTZ
Transmitter Supply Current Power Down =Low
10江志丰
55
µA
Power Down
Driver Outputs in TRI-STATE ®under Power Down Mode
RECEIVER SUPPLY CURRENT ICCRW
好久不见链接Receiver Supply Current C
L
=8pF,
f =32.5MHz 4965mA Worst Case
Worst Case Pattern
f =37.5MHz 5370mA (Figures 1,4),T A =−40˚C to +85˚C
f =65MHz 78105mA ICCRG
Receiver Supply Current,C
L
=8pF,
f =32.5MHz 2845mA 16Grayscale
16Grayscale Pattern
f =37.5MHz 3047mA (Figures 2,4),T A =−40˚C to +85˚C
f =65MHz
4360mA ICCRZ
Receiver Supply Current Power Down =Low
10
55
µA
Power Down
Receiver Outputs Stay Low during Power Down Mode
Note 1:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the device should be operated at these limits.The tables of “Electrical Characteristics”specify conditions for device operation.Note 2:Typical values are given for V CC =3.3V and T A =+25C.
Note 3:Current into device pins is defined as positive.Current out of device pins is defined as negativ
e.Voltages are referenced to ground unless otherwise specified (except V OD and ∆V OD ).Note 4:V OS previously referred as V CM .
Transmitter Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Symbol Parameter
Min Typ Max Units LLHT LVDS Low-to-High Transition Time (Figure 3)0.75  1.5ns LHLT LVDS High-to-Low Transition Time (Figure 3)0.75  1.5ns TCIT TxCLK IN Transition Time (Figure 5)5
ns TCCS TxOUT Channel-to-Channel Skew (Figure 6)
250
ps TPPos0Transmitter Output Pulse Position for Bit 0(Figure 17)f =65MHz −0.400.3ns TPPos1Transmitter Output Pulse Position for Bit 1  1.8  2.2  2.5ns TPPos2Transmitter Output Pulse Position for Bit 2  4.0  4.4  4.7ns TPPos3Transmitter Output Pulse Position for Bit 3  6.2  6.6  6.9ns TPPos4Transmitter Output Pulse Position for Bit 48.48.89.1ns TPPos5Transmitter Output Pulse Position for Bit 510.61111.3ns TPPos6Transmitter Output Pulse Position for Bit 612.813.213.5ns TCI
P TxCLK IN Period (Figure 7)15T 50ns TCIH TxCLK IN High Time (Figure 7)0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 7)0.35T
0.5T
0.65T
ns TSTC TxIN Setup to TxCLK IN (Figure 7)f =65MHz    2.5ns THTC TxIN Hold to TxCLK IN (Figure 7)
0ns
TCCD
TxCLK IN to TxCLK OUT Delay 25˚C,V CC =3.3V (Figure 9)
3.0
3.7
5.5
ns
D S 90C 383/D S 90C F 384
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DS90C383/DS90CF384 Transmitter Switching Characteristics(Continued)
Over recommended operating supply and−40˚C to+85˚C ranges unless otherwise specified
Symbol Parameter Min Typ Max Units TPLLS Transmitter Phase Lock Loop Set(Figure11)10ms
TPDD Transmitter Power Down Delay(Figure15)100ns Receiver Switching Characteristics
Over recommended operating supply and−40˚C to+85˚C ranges unless otherwise specified
Symbol Parameter Min Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time(Figure4)  2.2  5.0ns
CHLT CMOS/TTL High-to-Low Transition Time(Figure4)  2.2  5.0ns RSPos0Receiver Input Strobe Position for Bit0(Figure18)f=65MHz0.7  1.1  1.4ns RSPos1Receiver Input Strobe Position for Bit1  2.9  3.3  3.6ns RSPos2Receiver Input Strobe Position for Bit2  5.1  5.5  5.8ns RSPos3Receiver Input Strobe Position for Bit37.37.78.0ns RSPos4Receiver Input Strobe Position for Bit49.59.910.2ns RSPos5Receiver Input Strobe Position for Bit511.712.112.4ns RSPos6Receiver Input Strobe Position for Bit613.914.314.6ns RSKM RxIN Skew Margin(Note5)(Figure19)f=65MHz400ps RCOP RxCLK OUT Period(Figure8)15T50ns RCOH RxCLK OUT High Time(Figure8)f=65MHz7.38.6ns
RCOL RxCLK OUT Low Time(Figure8)  3.45  4.9ns
RSRC RxOUT Setup to RxCLK OUT(Figure8)  2.5  6.9ns RHRC RxOUT Hold to RxCLK OUT(Figure8)  2.5  5.7ns RCCD RxCLK IN to RxCLK OUT Delay25˚C,V CC=3.3V(Figure10)  5.07.19.0ns RPLLS Receiver Phase Lock Loop Set(Figure12)10ms RPDD Receiver Power Down Delay(Figure16)1µs
Note5:Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs.This margin takes into account the transmitter pulse positions(min
and max)and the receiver input setup and hold time(internal data sampling window-RSPOS).This ma
rgin allows for LVDS interconnect skew,inter-symbol interference(both dependent on type/length of cable),and clock jitter(less than250ps).
AC Timing Diagrams Array
DS012887-3
FIGURE1.“Worst Case”Test Pattern
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