TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6B70BFG
Interface IC for Hot Water Dispensers
The T6B70BFG is designed to be used mainly as an interface IC
我想去纽约for communication between hot water dispensers and the
corresponding controller unit, and comes equipped with a two channel 4-bit D/A converter, pseudo sine wave generator and an external analog signal detection circuit.
Features
• Built-in two channel 4-bit D/A converter (opposite polarities) • Built-in pseudo sine wave generator
(external clock 1/16 frequency divider)
• Built-in external analog signal detection/non-detection circuit • Built-in two channel analog switch
Block Diagram
Pin Assignment Diagram
Weight: 0.16 g (typ.)
OSCIN
OSCOUT FOUT /SCTL /RESET AMPOUT AMPIN V SS V DD SW1OUT SW1IN
SOUT + SOUT − SW2IN SW2OUT /DOUT
SOUT + SOUT −
李靓蕾家境富有V DD
AMPIN
AMPOUT
V SS /DOUT
Pin Functions
Pin No. Symbol Input/Output Function
1 OSCIN Input Pins connected to oscillation
2 OSCOUT Output Pins connected to oscillation
3 FOUT Output Output pin for oscillation waveform shaping circuit
4 /SCTL Input Modulation control signal input pin
5 /RESET Input Reset signal input pin
6 AMPOUT Output Amplifier signal output pin
7 AMPIN Input Amplifier signal input pin
8 V SS⎯Device ground pin (0 V)
9 /DOUT Output Output pin for amplifier input signal detector
10 SW2OUT Output Output pin on analog SW2 side
11 SW2IN Input Input pin on analog SW2 side
13 SOUT+Output Pseudo sine wave output pin
14 SW1IN Input Input pin on analog SW1 side
15 SW1OUT Output Output pin on analog SW1 side
16 V DD⎯ Device power supply pin (+5 V)
The equivalent circuit diagrams provided in the above table are given to facilitate understanding in designing the external circuitry but are not intended to accurately represent the internal circuitry.
Functions
1. Pseudo sine wave generator and 4-bit D/A converters (transmission block)
The pseudo sine wave signal with Fosc/16 frequency is output from the pseudo sine wave output pins (SOUT + and SOUT −).
The output polarity of SOUT + and SOUT − are the opposite.
The transmission block (pseudo sine wave generator and 4-bit D/A converter are as shown below (SOUT + pin side):
The data of the pseudo sine wave generator is output in the following sequence:男人装脱得最彻底女星
0 → 1 → 3 → 6 → 9 → C → E → F → F → E → C → 9 → 6 → 3 → 1 → 0 (hexadecimal)
Therefore, when there is no load, the pseudo sine waveform of the positive and negative output is like a staircase (as illustrated above).publicenemy
An analog switch is built-in so that the driver output buffer connects to the transmission line only during transmission.
However, an emitter follower circuit is externally connected to the driver output buffer.
The phase difference between the positive and negative output is within 180° ± 5° (to account for fluctuation in the pseudo sine wave output phase).
+ pin
F SOUT +
SOUT −
F F
@F OSC = 4 MHz
2. Amplifier input circuit and signal detection/non-detection circuit (reception block)
The modulation signal input block is equipped with high and a low comparator to detect only when the external sine wave signal’s amplitude is above the defined threshold. In this way, signals with amplitudes lower than the specified threshold (e.g., noise signals) are prevented from being mistakenly detected as sine waves.
The detection frequency range (frequency window) is determined by the divider ratio 1/17 to 1/15 of F osc
. Detection/non-detection confirmation conditions are such that when the signals within the specified
frequency range are detected (or not detected) in succession, the signals are controlled. It takes about 9 to 15 waves (based on F osc 1/16 frequency) to make detection/non-detection confirmation in this manner.
VH
VL
Reception detected AMP IN input sine waveform
Reception non-detected Reception non-detected Reception non-detected
VH VL
VH > VBIAS > VL VH > VBIAS > VL
AMPOUT output timing (/RESET = L)
AMPOUT Truth Table
赵姨娘是谁3. Transmission block function and timing
When the modulation control input (/SCTL) is in High-level, the pseudo sine wave output is held at 0° phase of the pseudo sine wave. When the modulation control input changes from High-level to Low-level, the pseudo sine wave output (SOUT +) initially outputs from -90° (SOUT − outputs from +90°). The time required to turn ON in this case is as follows: td (ON) < 500 ns
When modulation control input changes from Low-level to High-level, the phase is forcibly held at 0° (the pseudo sine wave output is stopped), regardless of the phase of the pseudo sine wave output. The time required to turn OFF in this case is as follows: td (OFF) < 1 μs
4. Reception block function and timing
Once it is okay to receive the amplifier input signal, the time it takes for the /DOUT pin to changes from High to Low (T (DET)) is about 9 to 15 waves (based on F osc 1/16 frequency). This condition is only valid when the cyclic input signal within the range specified by the frequency window is detected (or not detected) in continuation.
Note 1: You are free to use any kind of communication protocol you wish, however be sure to configure a time of
carrier wave × 15 waves or more for both when there are and aren’t signals.
/SCTL
SOUT +
(SOUT −Amplifier input
/DOUT
Timing Chart (SOUT+= SW1IN, SW1OUT, SOUT−= SW2IN, SW2OUT) V
SOUT
SOUT
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